1. Technical Field of the Invention
The present invention relates generally to semiconductor memories, and more particularly, to memory compilers for semiconductor memories having a block erase circuit that is used for clearing the memory array on a per I/O basis or any portion thereof.
2. Description of Related Art
For certain types of memories such as Cache Tags or Translation Lookaside Buffers (TLBs), it is highly desirable to be able to clear the array as quickly as possible, for example, during a context switch. Typically, these types of memories are relatively small compared to the cache memories they are associated with. For a chip that uses compilable memory (e.g., compilable static random access memory or SRAM) for its caches, it would be advantageous to be able to reset the memory (i.e., change the data state for all bits to a xe2x80x9c0xe2x80x9d) on a xe2x80x9cper I/Oxe2x80x9d basis, so that the Tags can be integrated in the same structure as the caches, sharing row decoders and other front end circuitry.
Several methods are known for block clear or reset of a memory. For example, in U.S. Pat. No. 4,780,847 to Ito, a method is disclosed for clearing a standard 6T SRAM cell by raising one of the VSS terminals in the cells to the VDD during the block clear operation. However, this method is applicable only to a 6T SRAM cell, with the further requirement that multiple VSS signals be supplied to each memory bit cell (typically with vertical metal lines parallel to the bitlines). Clearly, such limitations are disadvantageous for the high-speed, high density memory processes using 0.18 xcexcm or smaller geometries that are currently being employed, since the VSS line is often run in the middle of the cell rather than shared between adjacent cells as in typical topologies of previous generations.
Another technique for clearing a memory is disclosed in U.S. Pat. No. 4,928,266 to Abbott et al., wherein one or more xe2x80x9cresetxe2x80x9d transistors are added to the memory bit cell itself in order to force the memory bit cell to a known state with an active signal supplied to the additional transistors. This is typically done by converting one (or both for symmetry reasons) of the cross-coupled inverters in the memory bit cell to a NOR gate which drives the cell to a known state upon application of the reset signal to the gate of the additional transistor(s). It should be apparent that this method has the obvious disadvantage of adding a significantly greater area to the standard memory bit cell. Further, including a non-standard memory bit cell to obtain erase functionality means that this type of memory bit cell must be qualified from a manufacturability and reliability standpoint in addition to qualifying the normal (i.e., standard) memory bit cells, which entails significant work and additional time-to-market. Finally, in compiled memory architectures where the 1P memory bit cell is vertical and 2P cell is horizontal, the schedule penalty of re-laying out the pitched cells (e.g., X-decoders, Y-muxes, etc.) in both directions is severe for the NOR method.
Accordingly, the present invention advantageously provides a circuit for selectively erasing a semiconductor memory instance made up of standard memory bit cell topologies on a per I/O basis or any portion of the array, which overcomes these and other shortcomings and deficiencies of the current techniques. Preferably, the circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select all memory bit cells accessed by a particular I/O that is provided to be erasable. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, VDD, when a clear operation is to be performed. The I/O block is cleared by placing a predetermined logic state (typically 0) on the bitline nodes of the memory bit cells therein and selectively coupling the local wordlines to the VDD node. In other exemplary embodiments, the erasable I/Os of the entire memory array may be successively erased in staggered proportions (e.g., xe2x85x9th, xc2xcth, xc2xdth, etc.) by utilizing multiple clear signals, each being responsible for clearing a portion of the I/O, so as to spread out and reduce the peak value of the high current spike in the array.
In another aspect, the present invention is directed to a memory compiler for use in designing an integrated semiconductor device having an embedded memory instance that is selectively erasable. Included in the compiler architecture is a memory macro cell associated with the embedded memory instance, wherein the memory macro cell comprises an array core with a row decoder for generating global wordlines. At least one memory array I/O block includes a tilable circuit associated therewith to selectively erase memory bit cells therein. In a further exemplary embodiment, a driver circuit is included to disable a high voltage node (i.e., VDD node) associated with the memory bit cells in the I/O block so that the erase process does not have to contend with the internal electrical characteristics of the cells under an active VDD node.
In yet further aspect, the present invention is directed to a circuit provided as a repeatable architectural element in a memory compiler, wherein the circuit is used for selectively clearing an I/O block in a memory array. The circuit preferably comprises a plurality of pass gates disposed between global wordlines generated by a row decoder provided for the memory array and local wordlines provided selecting memory bit cells in the clearable I/O block. Memory clear logic is provided for selectively decoupling the local wordlines from the global wordlines so as to pull the local wordlines to a high voltage node. Memory bit cells coupled to the local wordlines are erased when a predetermined logic state is applied at bitline nodes of the memory bit cells of the I/O block and the local wordlines are pulled high as set forth above.